The gates

The kind of answer

Computed. A gate is arithmetic on true and false, and its truth table is worked out, not guessed. Morse already counts in twos. When you run a chip’s test, the comparison is found, as in Unit 3: it is a fact you look at, and it does not care what you hoped.

On paper first

NAND’s truth table: two inputs, four rows, and the output is 0 only when both inputs are 1. Then, still on paper, find how to make Not with one NAND, and And with two.

What you build

In the Hardware Simulator, choose Project 1 from the list at the top, then each chip in turn.

• Not
• And
• Or
• Xor
• Mux
• DMux
• Not16
• And16
• Or16
• Mux16
• Or8Way
• Mux4Way16
• Mux8Way16
• DMux4Way
• DMux8Way

Each one is done when its test passes in the IDE. A pass cannot be argued with, and neither can a fail.

Week by week

About an afternoon a week. If a week runs long, let it: the strand keeps its own order, not the calendar’s.

Week	Watch	Do
Week 4	1.1; 1.2	The truth tables of Not, And and Or, on paper. Then the trick from lecture 1.2: any truth table can be written as an Or of Ands.
Week 5	1.3; 1.4	How a chip is described in HDL. Write Not, And and Or in HDL on paper, before you touch the computer.
Week 6	1.5	The Hardware Simulator. Type in Not, And and Or, and run each one’s test until it passes. Then Xor.
Week 7	1.6; 1.7	Mux and DMux, on paper first: a Mux is a switch that chooses which input to pass on. Mux is the first real wall; take the week.
Week 8	—	Buses, sixteen wires at once: Not16, And16, Or16 and Mux16. Then Or8Way.
Week 9	1.8	Mux4Way16, Mux8Way16, DMux4Way and DMux8Way: chips built out of the chips you just made. Then the gates are finished, every one passing its test.

The lectures

8 lectures, about 128 minutes in all, by Nisan and Schocken. Watch with your parent, one or two at a sitting.

• 1.1 Boolean Logic 12:27
• 1.2 Boolean Functions Synthesis 9:50
• 1.3 Logic Gates 10:06
• 1.4 Hardware Description Language 18:29
• 1.5 Hardware Simulation 33:54
• 1.6 Multi-Bit Buses 8:54
• 1.7 Project 1 Overview 24:39
• 1.8 Perspectives 9:45

For the parent

HDL describes wiring; it is not a list of steps, so the order of its lines does not matter, and every wire between parts must have a name. Bit 0 of a bus is the rightmost bit, which trips everyone once. When a chip will not pass, go back to its truth table on paper before touching the code. Project 1 is the longest project in Part I, so it walks beside two units.